FIG. 1 shows a switching capacitor circuit according to the prior art. An ANALOG IN signal is connected by a first switch to the input of a Schmidt trigger circuit when a HOLD signal is active high. A second switch under the control of a CK1 signal connects the input of the Schmidt trigger to a first side of a capacitor CAP2 when CK1 is active high. A third switch under the control of a CK2 signal connects the first side of capacitor CAP2 to ground when CK2 is active high. The second side of CAP2 is connected directly to ground. Another capacitor CAP1 is connected between the input of the Schmidt trigger and ground.
The output of the Schmidt trigger is /EOC, a Not End Of Conversion signal. /EOC is both an output of the circuit and an input to an AND gate whose other input is the CK2 signal. The output of the AND gate is CK, which is also the clock input to a counter. The counter has a RESET input and produces as its output a DIGITAL COUNT signal. The DIGITAL COUNT signal is converted by a ROM lookup table into a DIGITAL VALUE corresponding to the voltage level of the ANALOG IN signal when /EOC goes low indicating that the analog to digital conversion process is complete.
FIG. 2 is a timing diagram illustrating the operation of the circuit shown in FIG. 1. As shown in FIG. 2, the HOLD, RESET, and CK2 signals initially all go high at the same time. The active high level of the HOLD signal connects the ANALOG IN signal to the input of the Schmidt trigger and CAP1, while the active high RESET signal resets the counter. The active high CK2 signal connects the first side of CAP2 to ground. Thus, at this time, CAP1 is charged to the voltage level of the ANALOG IN signal, CAP2 is discharged to ground, and the counter is reset. Since the counter is now reset, /EOC goes high at this time. A high /EOC and high CK2 enable the AND gate, and CK goes high for the duration of CK2.
After the activity just described, the HOLD, RESET, and CK2 signals return to their inactive low states, thereby opening the first and third switches and freeing the counter to count. Then, upon the occurrence of CK1 going active high, the second switch is closed, connecting CAP2 to CAP1. Since CAP2 is significantly smaller than CAP1, CAP2 now charges to nearly the original voltage level of CAP1, while CAP1 is slightly discharged in response. When CK1 returns to its inactive low state the charge on CAP2 is isolated. The next high on CK2 discharges CAP2 to ground, after which this cycle is repeated. Each time that CAP2 is charged and discharged the charge remaining on CAP1 is decreased. However, while the charge on CAP1 remains above the threshold of the Schmidt trigger, the output of the Schmidt trigger, /EOC, remains high and the AND gate remains enabled. And, while the AND gate is enabled, each time that CK2 goes high, the AND gate produces another active high CK signal, causing another count of the counter.
The DIGITAL COUNT final value that is present when /EOC goes low has a non-linear but monotonic relationship to the voltage level present at the ANALOG IN input when the HOLD signal caused it to be sampled. A low on /EOC acts as a read enable signal to the ROM lookup table to convert the DIGITAL COUNT value to a DIGITAL VALUE that is directly proportional to the ANALOG IN signal voltage level when it was sampled. The ROM lookup table values are determined empirically as part of an end-to-end initial calibration procedure, as is Well known in the art.
Because the switching capacitor circuit shown in FIG. 1 requires a fairly large number of clock (CK1, CK2, and CK) cycles to perform its function, it is relatively slow and therefore unsuitable for some applications.
U.S Pat. No. 5,144,525 to Saxe et al. for an "Analog Acquisition System Including a High Speed Timing Generator", hereby incorporated by reference, discloses an analog signal acquisition system which is suitable for use in a high speed analog oscilloscope. In this system, the input signal is rapidly and repetitively sampled by a succession of analog capture cells. The contents of these capture cells are then transferred to an array of analog memory cells as part of a fast-in, slow-out (FISO) system architecture. In such a system, a means is required for performing rapid analog-to-digital conversion of the numerous analog samples that are acquired with such rapidity.